Dynamic Cache Reconfiguration for Soft Real-Time Systems

被引:24
作者
Wang, Weixun [1 ]
Mishra, Prabhat [1 ]
Gordon-Ross, Ann [2 ]
机构
[1] Univ Florida, Dept Comp & Informat Sci & Engn, Gainesville, FL 32611 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
基金
美国国家科学基金会;
关键词
Design; Performance; Real-time systems; low-power; embedded systems; cache; ENERGY;
D O I
10.1145/2220336.2220340
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In recent years, efficient dynamic reconfiguration techniques have been widely employed for system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. It is a major challenge to introduce cache reconfiguration into real-time multitasking systems, since dynamic analysis may adversely affect tasks with timing constraints. This article presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during runtime to minimize energy while maintaining the same service level. To the best of our knowledge, this is the first attempt to integrate dynamic cache reconfiguration in real-time scheduling techniques. Our experimental results using a wide variety of applications have demonstrated that our approach can significantly reduce the cache energy consumption in soft real-time systems (up to 74%).
引用
收藏
页数:31
相关论文
共 43 条
[1]   Scheduling Arbitrary-Deadline Sporadic Task Systems on Multiprocessors [J].
Andersson, Bjoern ;
Bletsas, Konstantinos ;
Baruah, Sanjoy .
RTSS: 2008 REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2008, :385-+
[2]  
[Anonymous], 2004, P DES AUT TEST EUR C
[3]   A survey of design techniques for system-level dynamic power management [J].
Benini, L ;
Bogliolo, A ;
De Micheli, G .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (03) :299-316
[4]  
Burger D., 1996, EVALUATING FUTURE MI
[5]  
BUTTAZZO GC, 1995, HARD REAL TIME COMPU
[6]   Fast configurable-cache tuning with a unified second-level cache [J].
Gordon-Ross, A ;
Vahid, F ;
Dutt, N .
ISLPED '05: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, :323-326
[7]   Automatic tuning of two-level caches to embedded applications [J].
Gordon-Ross, A ;
Vahid, F ;
Dutt, N .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :208-213
[8]  
Gordon-Ross A, 2007, DES AUT TEST EUROPE, P755
[9]  
Hennessy JL, 2019, COMPUTER ARCHITECTUR
[10]   Power optimization of variable-voltage core-based systems [J].
Hong, I ;
Kirovski, D ;
Qu, G ;
Potkonjak, M ;
Srivastava, MB .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1999, 18 (12) :1702-1714