A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates

被引：14

作者：

Delatte, P ^{[1
]}

Picún, G ^{[1
]}

Demeûs, L ^{[1
]}

Simon, P ^{[1
]}

Flandre, D ^{[1
]}

机构：

[1] CISSOID SA, B-1348 Louvain, Belgium

来源：

ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSCIR.2005.1541643

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates (p > 1000 Omega.cm). It demonstrates the drastic improvement in the varactors and inductors quality factor on these substrates. It stresses on the importance of optimizing the tank inductor and the VCO for high-resitivity substrates. A 5GHz VCO designed in a 0.13 mu m Partially Depleted SOI CMOS confirms the low-power performance with a Figure-of-Merit greater than 190, placing this design at the top of the state-of-the-art.

引用

页码：395 / 398

页数：4

共 12 条

[1]

FONG N, 2002, S VLSI CIRC HON JUN

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