SKG-Lock+: A Provably Secure Logic Locking SchemeCreating Significant Output Corruption

被引:2
作者
Nguyen, Quang-Linh [1 ,2 ]
Dupuis, Sophie [1 ]
Flottes, Marie-Lise [1 ]
Rouzeyre, Bruno [1 ]
机构
[1] Univ Montpellier, Lab Informat Robot & Microelect Montpellier, CNRS, F-34095 Montpellier 5, France
[2] STMicroelectronics, 12 Rue Jules Horowitz, F-38019 Grenoble, France
关键词
logic locking; SAT attack; Design-for-Trust; hardware security; IP protection; overproduction; SAT ATTACK;
D O I
10.3390/electronics11233906
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent countermeasure to tackle this threat in particular. Logic locking consists of "locking" an IC with an added primary input, the so-called key, which, unless fed with the correct secret value, renders the ICs unusable. One of the first criteria ensuring the quality of a logic locking technique was the output corruption, i.e., the corruption at the outputs of a locked circuit, for any wrong key value. However, since the introduction of SAT-based attacks, resulting countermeasures have compromised this criterion in favor of a better resilience against such attacks. In this work, we propose SKG-Lock+, a Provably Secure Logic Locking scheme that can thwart SAT-based attacks while maintaining significant output corruption. We perform a comprehensive security analysis of SKG-Lock+ and show its resilience against SAT-based attacks, as well as various other state-of-the-art attacks. Compared with related works, SKG-Lock+ provides higher output corruption and incurs acceptable overhead.
引用
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页数:24
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