How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices have been found to be accidentally triggered on by noise pulses when IC's are operated in the normal operating condition. A stacked design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS IC's without causing unexpected operation errors or latchup danger. Such stacked LVTSCR's with a holding voltage greater than VDD of IC's can provide CMOS IC's with effective component-level ESD protection but without being accidentally triggered on by system-level overshooting or undershooting noise pulses. (C) 1999 Elsevier Science B.V. All rights reserved.