3DES Implementation Based on FPGA

被引：0

作者：

Ren, Fang ^{[1
]}

Chen, Leihua ^{[1
]}

Zhang, Tao ^{[2
]}

机构：

[1] Shaanxi Meteorol Serv, Meteorol Sci & Technol Serv Ctr, Sian 710014, Shaanxi, Peoples R China

[2] Lighting Proof Technol Ctr, Shangqiu Meteorol Ser, Henan, Peoples R China

来源：

EMERGING RESEARCH IN WEB INFORMATION SYSTEMS AND MINING | 2011年 / 238卷

关键词：

3DE; FPGA; finite state machine; pipeline; VHDL;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In order to meet the demand of plenty continuous encrypting-deciphering, and meet the demand of enhancing the security of encrypting-deciphering algorithm, the fundamental technologies such as pipeline technology and finite state machine (FSM) are applied, 3DES encryption algorithm's encryption chip's circuit based on FPGA are designed and realized. On the platform of FPGA of Xilinx Virtex4 series, the ISE 10.1 development kits are used to realize the simulation confirmation and the logic synthesis. The result indicates that the 3DES cryptographic system's speed is able to achieve 860.660Mbps and the encrypting-deciphering speed is greatly enhanced. The design could be used in network security products and other security equipment extensively.

引用

页码：218 / +

页数：2