A 1.4 pJ/bit, Power-Scalable 16x12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

被引：26

作者：

Dickson, Timothy O. ^{[1
]}

Liu, Yong ^{[1
]}

Rylov, Sergey V. ^{[1
]}

Agrawal, Ankur ^{[1
]}

Kim, Seongwon ^{[1
]}

Hsieh, Ping-Hsuan ^{[1
]}

Bulzacchelli, John F. ^{[1
]}

Ferriss, Mark ^{[1
]}

Ainspan, Herschel A. ^{[1
]}

Rylyakov, Alexander ^{[1
]}

Parker, Benjamin D. ^{[1
]}

Beakes, Michael P. ^{[1
]}

Baks, Christian ^{[1
]}

Shan, Lei ^{[1
]}

Kwark, Young ^{[1
]}

Tierno, Jose A. ^{[1
]}

Friedman, Daniel J. ^{[1
]}

机构：

[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2015年 / 50卷 / 08期

关键词：

Clock distribution; CTLE; DFE; I/O; phase rotator; serializer; source synchronous; 10-GB/S; TRANSCEIVER; FFE;

D O I：

10.1109/JSSC.2015.2412688

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75" Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20" Megtron-6 PCB traces.

引用

页码：1917 / 1931

页数：15

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