Vertical wrap-gated nanowire transistors

被引：141

作者：

Bryllert, T

Wernersson, LE

Löwgren, T

Samuelson, L

机构：

[1] Lund Univ, Dept Solid State Phys, Nanometre Struct Consortium, SE-22100 Lund, Sweden

[2] Lars Ake Ledebo, QuNano AB, SE-22224 Lund, Sweden

[3] Chalmers Univ Technol, Microwave Elect Lab, Dept Microtechnol & Nanosci, SE-41296 Gothenburg, Sweden

来源：

NANOTECHNOLOGY | 2006年 / 17卷 / 11期

关键词：

D O I：

10.1088/0957-4484/17/11/S01

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

We present a process for fabricating a field-effect transistor based on vertically standing InAs nanowires and demonstrate initial device characteristics. The wires are grown by chemical beam epitaxy at lithographically defined locations. Wrap gates are formed around the base of the wires through a number of deposition and etch steps. The fabrication is based on standard III - V processing and includes no random elements or single nanowire manipulation.

引用

页码：S227 / S230

页数：4

共 8 条

[1]

BRYLLERT T, 2005, IEEE DEV RES C DRC

[2] Benchmarking nanotechnology for high-performance and low-power logic transistor applications [J].