An Enabling Device Technology for Future Superjunction Power Integrated Circuits

The lateral superjunction power MOSFET device fabricated on the bulk silicon substrate suffers from the substrate-assisted depletion effect, which causes charge imbalance and thus limits the sustainable voltage rating. An enabling device technology, which is fully integrated on the partial Silicon on Insulator (PSOI) platform using the bulk silicon substrate, is described in this paper. The new technology has the potential to eliminate the substrate-assisted depletion. It enables the implementation of lateral superjunction power MOSFET (SJ LDMOS) on bulk silicon substrate without sacrificing its electrical and thermal performance. The approach was demonstrated successfully on both planar and trench gate SJ LDMOS devices. At the given breakdown voltage rating, the drift region doping concentration can be raised to one order higher than that of the conventional LDMOS. The proposed technology has enabled the fabrication of SJ power integrated circuits on the bulk silicon substrate for future automotive power electronics applications.