A 3.5-6.8GHz Wide-band width DTC-assisted Fractional-N All-digital PLL with a MASH ΔΣ TDC for Low In-Band Phase Noise

被引：0

作者：

Wu, Ying ^{[1
]}

Shahmohammadi, Mina ^{[1
]}

Chen, Yue ^{[1
]}

Lu, Ping ^{[2
]}

Staszewski, Robert Bogdan ^{[1
,3
]}

机构：

[1] Delft Univ Technol, NL-2600 AA Delft, Netherlands

[2] Lund Univ, S-22100 Lund, Sweden

[3] Univ Coll Dublin, Dublin, Ireland

来源：

ESSCIRC CONFERENCE 2016 | 2016年

关键词：

All digital PLL; noise shaping; DTC; MASH; TDC; wide-tuning range; wide-bandwidth; BBPD; DCO;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH Delta Sigma time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40-nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a divided by 2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fs(rms) integrated jitter.

引用

页码：209 / 212

页数：4

共 6 条

[1]

Chillara V.K., 2012, ISSCC, P172

[2] A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC [J].