Improved performance of fully-recessed normally-off LPCVD SiN/GaN MISFET using N2O plasma pretreatment

An effective and simple approach for gate-recessed normally-off GaN-based MISFETs is proposed to suppress the high temperature induced degradation during low pressure chemical vapour deposition (LPCVD) in gate-recessed normally off GaN-based MISFET. After a N2O plasma treatment on GaN channel prior to LPCVD SiN, the LPCVD SiN/GaN MISFET exhibits a maximum drain current of 607 mA/mm, 3 times higher than that without N2O plasma pretreatment, a threshold voltage of + 1.2 V at I-D = 0.1 mA/mm, off-state hard-breakdown voltage of 1348 V with L-GD = 20 mu m, and gate leakage current below 15 nA/mm in the whole gate swing to + 20 V. The interface states characterization in MISFETs show that about 3 times lower interface trap density was achieved in MISFET with N2O plasma pretreatment compared to that in SiNx/GaN transistor without such surface treatment.