High Speed Copper Electrodeposition for Through Silicon Via(TSV)

被引:2
作者
Kondo, Kazuo [1 ]
Suzuki, Yushi [1 ]
Saito, Takeyasu [1 ]
Okamoto, Naoki [1 ]
机构
[1] Osaka Prefecture Univ, Dept Chem Engn, Sakai, Osaka 5998531, Japan
来源
PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS | 2010年 / 25卷 / 38期
关键词
3-DIMENSIONAL CHIP STACKING; ASPECT-RATIO COPPER;
D O I
10.1149/1.3390665
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
Copper electrodeposition in high aspect ratio via is one of the key technologies for 3D packaging. High speed copper electrodeposition is needed to achieve high TSV throughput. To inhibit the top surface of TSV, the ODT, was micro contact printed on the chip surface. ODT micro contact printing effectively inhibits the copper electrodepositon at the top surface. With SDDAC, V-shapes were formed in the via cross section and these V-shape shapes lead to bottom up via filling. Since the current density is lower for higher rotation disk rotation speed from the potential-current density curves, the copper electrodeposition is inhibited at the via openings. This leads to the V-shape cross sections. We succeeded to fill the 10 mu m in diameter and 70 mu m in depth via within 37 minutes. This was achieved with shortening the off time to 100ms, ODT micro contact printing and adding 1mg/L of SDDACC additive.
引用
收藏
页码:127 / 131
页数:5
相关论文
共 7 条
  • [1] ASET, 1999, ANN REPORTS ELECT SI
  • [2] Casimirus S., 2009, S P 3D CHIP STACK EL, P106
  • [3] Additive-free superfilling in damascene Cu Electrodeposition using microcontact printing
    Kim, SK
    Kim, JJ
    [J]. ELECTROCHEMICAL AND SOLID STATE LETTERS, 2004, 7 (09) : C101 - C103
  • [4] High-aspect-ratio copper-via-filling for three-dimensional chip stacking - II. Reduced electrodeposition process time
    Kondo, K
    Yonezawa, T
    Mikami, D
    Okubo, T
    Taguchi, Y
    Takahashi, K
    Barkey, DP
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2005, 152 (11) : H173 - H177
  • [5] Lun O., 2008, EL COMP TECHN C MAY, P866
  • [6] High-aspect-ratio copper via filling used for three-dimensional chip stacking
    Sun, JJ
    Kondo, K
    Okamura, T
    Oh, SJ
    Tomisaka, M
    Yonemura, H
    Hoshino, M
    Takahashi, K
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2003, 150 (06) : G355 - G358
  • [7] Process integration of 3D chip stack with vertical interconnection
    Takahashi, K
    Taguchi, Y
    Tomisaka, M
    Yonemura, H
    Hoshino, M
    Ueno, M
    Egawa, Y
    Nemoto, Y
    Yamaji, Y
    Terao, H
    Umemoto, M
    Kameyama, K
    Suzuki, A
    Okayama, Y
    Yonezawa, T
    Kondo, K
    [J]. 54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 601 - +