Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers

被引：8

作者：

Lin, S. H. ^{[1
]}

Yang, H. J. ^{[2
]}

Chen, W. B. ^{[2
]}

Yeh, F. S. ^{[1
]}

McAlister, Sean P. ^{[3
]}

Chin, Albert ^{[2
,4
]}

机构：

[1] Natl Tsing Hua Univ, Inst Elect Engn, Dept Elect Engn, Hsinchu 300, Taiwan

[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[3] Natl Res Council Canada, Inst Microstruct Sci, Ottawa, ON K1A 0R6, Canada

[4] Nanoelect Consortium Taiwan, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 07期

关键词：

erase; high-kappa; nonvolatile memory; program;

D O I：

10.1109/TED.2008.924435

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have studied the performance of double-quantum-barrier [TaN - Ir3Si] - [HfAlO - LaAlO3] - Hf0.3N0.2O0.5 - [HfAlO - SiO2]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.

引用

页码：1708 / 1713

页数：6

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