Design of CMOS Low-Dropout Voltage Regulator for Power Management Integrated Circuit in 0.18-μm Technology

被引:1
作者
Murad, S. A. Z. [1 ]
Harun, A. [1 ]
Isa, M. N. M. [1 ]
Mohyar, S. N. [1 ]
Sapawi, R. [2 ]
Karim, J. [3 ]
机构
[1] Univ Malaysia Perlis, Sch Microelect Engn, Kampus Pauh Putra, Arau 02600, Perlis, Malaysia
[2] Univ Malaysia Sarawak, Dept Elect & Elect Engn, Fac Engn, Sarawak 94300, Malaysia
[3] Univ Teknol MARA, Fac Elect Engn, Shah Alam 40450, Selangor, Malaysia
来源
2ND INTERNATIONAL CONFERENCE ON APPLIED PHOTONICS AND ELECTRONICS 2019 (INCAPE 2019) | 2020年 / 2203卷
关键词
D O I
10.1063/1.5142098
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A low-dropout (LDO) voltage regulator is the main component used in the majority of portable electronic application since it is used as power management unit in those applications. In this paper, a LDO regulator for the power management integrated circuit in 0.18-mu m CMOS technology using Cadence software is presented. The error amplifier of the proposed LDO employed seven transistors for current mirror. Meanwhile, the PMOS transistor is used as a pass element transistor to control the voltage variation. The resistors are used as a feedback network circuit while the capacitor is used to minimise the variation of output voltage. The simulation results show that the proposed design provides a 2.41 V constant output voltage for the supply voltage ranges of 2.55 V to 3.55 V. The dropout voltage of 140 mV is achieved with 1.48 mW power consumption. The line regulation is 1.0 mV/V and the load regulation is 0.41 mV/A, while the layout of the proposed regulator is 27 mu m x 34 mu m.
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页数:8
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