Architecture Design Trade-offs among VLIW SIMD and Multi-core schemes

被引:1
作者
Wang, Yaohua [1 ]
Chen, Shuming [1 ]
Zhang, Kai [1 ]
Chen, Hu [1 ]
Chen, Xiaowen [1 ]
机构
[1] Natl Univ Def Technol, Sch Comp, Changsha, Hunan, Peoples R China
来源
2012 IEEE 26TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS & PHD FORUM (IPDPSW) | 2012年
关键词
VLIW; SIMD; multi-core; analytical model;
D O I
10.1109/IPDPSW.2012.206
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Hybrid architectures combined of VLIW, SIMD and multi-core schemes are increasingly prevailing in media processors, due to the abundant parallelism existed in media applications. However, parameters for current combinations such as the VLIW length, SIMD width and core count are set mainly according to simple profiling or the designer's experience rather than a systematic and in-depth investigation. With the development of both the application and the design technologies, a large amount of parallelism, together with better availability of computation resources motivate the need for deeper insight into the trade-offs among VLIW, SIMD and multi-core schemes. In this paper, an analytical model is proposed for these combinational architectures; furthermore, the area cost and cycle time variation are also provided in the form of different design constraints, under which, decent trade-offs are obtained, providing valuable insights into the design of media processors.
引用
收藏
页码:1649 / 1658
页数:10
相关论文
共 20 条
  • [1] AMDAHL G.M., 1967, P AFIPS C
  • [2] Bell S., 2008, SOL STAT CIRC C ISSC
  • [3] Corbal Jesus, 2001, HPCA
  • [4] Faraboschi P, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P203, DOI [10.1145/342001.339682, 10.1109/ISCA.2000.854391]
  • [5] Ge Rong, 2009, PAR DISTR PROC 2009
  • [6] Hennessy J., 2007, Computer Architecture-A Quantitative Approach
  • [7] Amdahl's law in the multicore era
    Hill, Mark D.
    Marty, Michael R.
    [J]. COMPUTER, 2008, 41 (07) : 33 - +
  • [8] Huang Libo, 2010, HPCA
  • [9] Kapasi U.J., 2000, MICROARCHITECTURE
  • [10] The vector-thread architecture
    Krashinsky, R
    Batten, C
    Hampton, M
    Gerding, S
    Pharris, B
    Casper, J
    Asanovic, K
    [J]. IEEE MICRO, 2004, 24 (06) : 84 - 90