III-V Complementary Metal-Oxide-Semiconductor Electronics on Silicon Substrates

被引：83

作者：

Nah, Junghyo ^{[1
,2
,3
]}

Fang, Hui ^{[1
,2
,3
]}

Wang, Chuan ^{[1
,2
,3
]}

Takei, Kuniharu ^{[1
,2
,3
]}

Lee, Min Hyung ^{[1
,2
,3
]}

Plis, E. ^{[4
]}

Krishna, Sanjay ^{[4
]}

Javey, Ali ^{[1
,2
,3
]}

机构：

[1] Univ Calif Berkeley, Berkeley, CA 94720 USA

[2] Lawrence Berkeley Natl Lab, Div Mat Sci, Berkeley, CA 94720 USA

[3] Univ Calif Berkeley, Berkeley Sensor & Actuator Ctr, Berkeley, CA 94720 USA

[4] Univ New Mexico, Albuquerque, NM 87106 USA

来源：

NANO LETTERS | 2012年 / 12卷 / 07期

关键词：

III-V CMOS; InAs; InGaSb; two-dimensional semiconductors; logic gate;

D O I：

10.1021/nl301254z

中图分类号：

O6 [化学];

学科分类号：

0703 ;

摘要：

One of the major challenges in further advancement of RI V electronics is to integrate high mobility complementary transistors on the same substrate. The difficulty is due to the large lattice mismatch of the optimal p- and n-type III-V semiconductors. In this work, we employ a two-step epitaxial layer transfer process for the heterogeneous assembly of ultrathin membranes of III-V compound semiconductors on Si/SiO2 substrates. In this III-V-on-insulator (XOI) concept, ultrathin-body InAs (thickness, 13 nm) and InGaSb (thickness, 7 nm) layers are used for enhancement-mode n- and p- MOSFETs, respectively. The peak effective mobilities of the complementary devices are similar to 1190 and similar to 370 cm(2)/(V s) for electrons and holes, respectively, both of which are higher than the state-of-the-art Si MOSFETs. We demonstrate the first proof-of-concept III-V CMOS logic operation by fabricating NOT and NAND gates, highlighting the utility of the XOI platform.

引用

页码：3592 / 3595

页数：4

共 25 条

[11] Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics [J].