Wideband Signal Synthesis Using Interleaved Partial-Order Hold Current-Mode Digital-to-Analog Converters

被引：12

作者：

Jha, Anuranjan ^{[1
]}

Kinget, Peter R. ^{[1
]}

机构：

[1] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2008年 / 55卷 / 11期

基金：

美国国家科学基金会;

关键词：

Digital-to-analog converter (DAC); sine filter; time interleaving; wideband signal synthesis; windowed integration;

D O I：

10.1109/TCSII.2008.2004538

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe how a zero-order hold digital-to-analog converter (DAC) followed by a windowed-integration-based filter results in a novel partial-order hold (POH) DAC architecture with the ability of broadband image reduction between 1.5 and two times the sampling frequency while also providing a flat-group delay. Interleaving two such POH-DACs results in a DAC with an excellent output signal reconstruction whereby the broadband sampling images below two times the sampling frequency in the output signal spectrum are strongly reduced. Some implementation techniques are proposed and the effect of implementation nonidealities is evaluated.

引用

页码：1109 / 1113

页数：5

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