Trends of on-chip interconnects in deep sub-micron VLSI

被引：3

作者：

Antono, DD ^{[1
]}

Inagaki, K

Kawaguchi, H

Sakurai, T

机构：

[1] Univ Tokyo, Tokyo 1538505, Japan

[2] Kobe Univ, Kobe, Hyogo 6578501, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2006年 / E89C卷 / 03期

关键词：

on-chip interconnects; deep sub-micron; inductive effect; signal integrity;

D O I：

10.1093/ietele/e89-c.3.392

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.

引用

页码：392 / 394

页数：3

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