Fabrication of patterned graphene FETs array

A new approach of fabrication of back-gated graphene FETs array based on the nano-wall channel between the source and the drain were investigated. Patterned metal film on three-dimentional nano-wall structure prepared by photo lithography was used as the source and the drain to bond the graphite foil. With SU-8 process in MEMS and lift off processes, metal is sputtered exactly onto the SU-8 patterns and forms electrodes. The potential transistor design relying only on a single sheet could be achieved by placing the graphene sheet film on the nano-wall channel between the source and the drain. Chemically derived graphene samples are then transferred onto 300nm SiO2/highly doped Si which serves as the back gate. A gas sensing region is expected to be present because the graphene sheet segment has great adsorption capacity of gas with the help of the nano-wall structure betwee the source and the drain strips. This method has offered potential convenience for future research on graphene properties, such as the anomalously quantized Hall effects, large charge carrier mobility and so on, and demonstrated a great potential application of novel structured FETs based on graphene. (C) 2012 Published by Elsevier B.V. Selection and/or peer review under responsibility of Chinese Vacuum Society (CVS).