Interface States Characterization of UTB SOI MOSFETs From the Subthreshold Current

被引：6

作者：

Vermeer, Matthias L. ^{[1
,2
]}

Hueting, Raymond J. E. ^{[1
]}

Pirro, Luca ^{[3
]}

Hoentschel, Jan ^{[3
]}

Schmitz, Jurriaan ^{[1
]}

机构：

[1] Univ Twente, MESA Inst Nanotechnol, NL-7500 AE Enschede, Netherlands

[2] Hamburg Univ Technol, Inst Microsyst Technol E 7, D-21073 Hamburg, Germany

[3] GlobalFoundries, D-01109 Dresden, Germany

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2021年 / 68卷 / 02期

关键词：

Ideality; interface states; MOS transistors; silicon devices; silicon on insulator; subthreshold; traps; LOW-FREQUENCY NOISE; TRAP DENSITY; THIN-FILM; THRESHOLD VOLTAGE; FRONT; SLOPE; EXTRACTION;

D O I：

10.1109/TED.2020.3043223

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Quantification of interface traps for double-gate fully depleted silicon-on-insulator transistors is needed for accurate device modeling and technology development. The trap density can be estimated as a function of the activation energy from the subthreshold current using the methodology developed in this work. It combines the earlier proposed g(m)/I-D method with a revised form of the k- sweep method. The method is verified using TCAD simulated data and applied on engineering samples produced in 22FDX (R) technology, yielding a typical trap density of 2 center dot 10(11) cm(-2)eV(-1). Association of the traps to the front or back interface is nontrivial; a trap allocation error of at least 20% is reported.

引用

页码：497 / 502

页数：6

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