Between-core vector overlapping for efflicient core testing of system-on-chip LSI circuits

In this paper, the authors propose a method for efficient parallel core testing for manufacturing testing of system-on-chip LSIs that consist of multiple full-scan cores; this method is called "between-core vector overlapping." To shorten the time needed to test the entire SoC LSI, this uses a single bit sequence for test data (overlapped vector) obtained by overlapping test vectors of multiple cores as much as possible; during testing, this is fed jointly to each core, so that multiple cores can be tested in parallel. A key benefit of this method is that it minimizes the number of external input pins needed for testing multiple cores in parallel. To further reduce test times, the authors also propose methods for shortening the overlapped vectors: invert overlapping and split overlapping. Tests show these methods to be effective. (C) 2006 Wiley Periodicals, Inc.