A switched OpAmp based 10 bits integrated ADC for ultra low power applications

被引：0

作者：

Bonfini, Giuseppe ^{[1
]}

Brogna, Andrea S. ^{[1
]}

Saletti, Roberto ^{[1
]}

Garbossa, Cristian ^{[2
]}

Colombini, Luca ^{[2
]}

Bacci, Maurizio ^{[2
]}

Chicca, Stefania ^{[2
]}

Bigongiari, Franco ^{[2
]}

机构：

[1] Univ Pisa, Dipartimento Ingn Informaz Elettron Informat Tele, Via G Caruso 2, I-56122 Pisa, Italy

[2] Aurelia Microelect, I-55049 Viareggio, Italy

来源：

VLSI-SOC: FROM SYSTEMS TO CHIPS | 2006年 / 200卷

关键词：

ultra low power; biomedical implantable applications; switched OpAmp; analog to digital converter;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an ultra low-power switched opamp-based integrated ADC designed using a cyclic algorithm approach, for cardiac pacemaker applications. The AID converter shows a typical operating power consumption of 8.18 mu W for the analog part and of 9.71 mu W for the digital one, whereas the stand by dissipation is about 1 nW and 5 nW, respectively, (measured on 10 chip samples and averaged), considering a typical supply of 2.8 V. The ADC resolution is 10 b, its typical operating clock frequency is 32 kHz (sampling rate is 2.9 kSamples/s) and it is able to reach the same resolution at 2 V with 0. 7 kSamples/s sampling rate, showing a dissipation of 1 mu W for the analog part and 1. 3 14 mu W for the digital part. Moreover, it is also characterized by low offset and no missing codes.

引用

页码：133 / +

页数：3

共 11 条

[1]

[Anonymous], IEEE J SOLID STATE C

[2]

BACHIROTTO A, 1997, P ISSCC C S FRANC, P58

[3] DESIGN STRATEGY FOR LOW-VOLTAGE SC CIRCUITS [J].