Modeling of nanoscale gate-all-around MOSFETs

被引：132
作者：
Jiménez, D
Sáenz, JJ
Iñíguez, B
Suñé, J
Marsal, LF
Pallarès, J
机构：
[1] Univ Autonoma Barcelona, Escola Tecn Super Engn, Dept Elect Engn, Barcelona, Spain
[2] Univ Autonoma Barcelona, Dept Fis Mat Condensada, Fac Ciencias, Barcelona, Spain
[3] Univ Rovira & Virgili, Escola Tecn Super Engn, Dept Engn Elect, Barcelona, Spain
来源：
IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 05期
关键词：
modeling; MOSFETs; quantum wires;
D O I：
10.1109/LED.2004.826526
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a compact physics-based model for the nanoscale gate-all-around MOSFET working in the ballistic limit. The current through the device is obtained by means of the Lan-dauer approach, being the barrier height the key parameter in the model. The exact solution of the Poisson's equation is obtained in order to deal with all the operation regions tracing properly the transitions between them.
引用
收藏
页码：314 / 316
页数：3
相关论文
共 9 条
[1]  
[Anonymous], 1999, PHYS LOW DIMENSIONAL
[2]   ON THE SOLUTION OF THE POISSON-BOLTZMANN EQUATION WITH APPLICATION TO THE THEORY OF THERMAL EXPLOSIONS [J].
CHAMBRE, PL .
JOURNAL OF CHEMICAL PHYSICS, 1952, 20 (11) :1795-1797
[3]  
Chen Y., 2001, P INT C MOD SIM MICR, P546
[4]   A silicon quantum wire transistor with one-dimensional subband effects [J].
Je, M ;
Han, S ;
Kim, I ;
Shin, H .
SOLID-STATE ELECTRONICS, 2000, 44 (12) :2207-2212
[5]   Compact modeling of nanoscale MOSFETs in the ballistic limit [J].
Jiménez, D ;
Sáenz, JJ ;
Iñíguez, B ;
Suñé, J ;
Marsal, LF ;
Pallarès, J .
ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, :187-190
[6]   Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field-effect-transistor [J].
Jiménez, D ;
Sáenz, JJ ;
Iñíquez, B ;
Suñé, J ;
Marsal, LF ;
Pallarès, J .
JOURNAL OF APPLIED PHYSICS, 2003, 94 (02) :1061-1068
[7]   BALLISTIC METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR [J].
NATORI, K .
JOURNAL OF APPLIED PHYSICS, 1994, 76 (08) :4879-4890
[8]   Multiple-gate SOI MOSFETs: Device design guidelines [J].
Park, JT ;
Colinge, JP .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (12) :2222-2229
[9]   Beyond the conventional transistor [J].
Wong, HSP .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2002, 46 (2-3) :133-168
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