Design and parallel computation of regularised fast Hartley transform

被引:5
|
作者
Jones, KJ [1 ]
机构
[1] TRL Technol Ltd, Tewkesbury GL20 8ND, Glos, England
来源
关键词
D O I
10.1049/ip-vis:20045066
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The paper describes the design and parallel computation of a regularised fast Hartley transform (FHT), to be used for computation of the discrete Fourier transform (DFT) of real-valued data. For the processing of such data, the FHT has attractions over the fast Fourier transform (FFT) in terms of reduced arithmetic operation counts and reduced memory requirement, whilst its bilateral property means it may be straightforwardly applied to both forward and inverse DFTs. A drawback, however, of conventional FHT algorithms lies in the loss of regularity arising from the need for two sizes of 'butterfly' for efficient fixed-radix implementations. A generic double butterfly is therefore developed for the radix-4 FHT which overcomes the problem in an elegant fashion. The result is a recursive single-butterfly solution, referred to as the regularised FHT, which lends itself naturally to parallelisation and to mapping onto a regular computational structure for implementation with algorithmically specialised hardware.
引用
收藏
页码:70 / 78
页数:9
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