Integration of alternative higk-K gate dielectrics into aggressively scaled CMOS Si devices: Chemical bonding constraints at Si-dielectric interfaces

Optimization of performance and reliability for aggressively-scaled CMOS FETs with high capacitance dielectrics (t(ox-eq) < 2 nm) can proceed in two steps i) first scaling to t(ox-eq) -1.2-1.5 nm using stacked oxide/nitride gate dielectrics with nitrogen profiles controlled at the atomic layer level, and ii) then to t(ox-eq) < 1 by using other alternative high-K gate dielectrics such as Ta2O5, Zr(Hf)O-2-SiO2 alloys and Al2O3 in stacked structures with hyper-thin (< 0.5 nm) nitrided oxide interfaces. This paper addresses three aspects of chemical bonding that are important for the implementation of alternative gate dielectrics: i) the balance between interfacial electronic and nuclear charge, ii) mechanical constraints imposed by average interfacial bonding coordination, and iii) interfacial band offset energies, primarily between the conduction bands of Si and the gate dielectric. These bonding constraints are applied to alternative gate dielectrics including i) oxide/nitride gate stacks, ii) Ta2O5, iii) Zr(Hf)O-2-SiO2 alloys acid iv) Al2O3, each requiring hyper-thin nitrided SiO2 interfaces.