Void free filling of TSV vias by bottom up copper electroplating for wafer level MEMS vacuum packaging

被引:0
|
作者
Xu, Chunlin [1 ]
Wang, Xuefang [1 ]
Wang, Yuzhe [1 ]
Xu, Minghai [1 ]
Hu, Chang [1 ]
Liu, Sheng [1 ]
机构
[1] Huazhong Univ Sci & Technol, Inst Microsyst, Stat Key Lab Digital Mfg Equipment & Technol, Sch Mech Sci & Engn, Wuhan 430074, Peoples R China
来源
2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012) | 2012年
关键词
FABRICATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Through silicon via (TSV) is an emerging technology for MEMS packaging for MEMS packaging. 370 mu m deep TSV vias with diameter of 60 mu m were filled by bottom up copper electroplating with copper methylsulfonate and methane sulfonic acid as base electrolyte. Insulating layer of the wafer was silicon nitride deposited by LPCVD. The TSV vias filling processes include electroplating to fill the vias and wet etching to remove the seed layer and adhesion layer. Patterned photoresist mask was adopted to obtain ideal electroplating results and protect the copper in the vias during the wet etching process. The copper filled wafer with silicon nitride was bonded with Pyrex_7740 glass having cavities by anodic bonding. The results of Helium pressure tests showed that the leak rate was less than 3*10(-9) Pa . m(3)/s. The results suggested the potential of TSV application in wafer level MEMS vacuum packaging.
引用
收藏
页码:64 / 67
页数:4
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