Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop

被引:1
作者
Ko, J. [1 ]
Heo, M. [1 ]
Lee, J. [2 ]
Kim, C. [2 ]
Lee, M. [1 ]
机构
[1] GIST, Sch Elect Engn & Comp Sci, Gwangju, South Korea
[2] ETRI, Deajeon, South Korea
关键词
current-mode circuits; compensation; digital phase locked loops; frequency; 2; MHz; gain; 7; 89; dB; 18; 57; digital compensation; phase rotator; deterministic phase error; CMPI; current-mode phase interpolator; fractional-N phase-locked loop; all-digital phase-locked loop; phase dithering; fractional spur reduction technique; PLL;
D O I
10.1049/el.2016.2098
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A spur reduction technique in fractional-N phase-locked loops based on a current-mode phase interpolator (CMPI) is presented by dithering input signals of the CMPI. CMPI shows deterministic phase error having symmetrical profile around 45 degrees offset in each quadrant, and this non-linear property leads to fractional spurs. The proposed 45 degrees phase rotator with digital compensation reduces the fractional spur by 18.57 dB at most, and average improvement of fractional tones is 7.89 dB in 2 MHz frequency step measurement.
引用
收藏
页码:1920 / 1922
页数:2
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