A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

被引：9

作者：

Nguyen, Nhat ^{[1
]}

Frans, Yohan ^{[1
]}

Leibowitz, Brian ^{[1
]}

Li, Simon ^{[1
]}

Navid, Reza ^{[1
]}

Aleksic, Marko ^{[1
]}

Lee, Fred ^{[1
]}

Quan, Fredy ^{[1
]}

Zerbe, Jared ^{[1
]}

Perego, Rich ^{[1
]}

Assaderaghi, Fari ^{[1
]}

机构：

[1] Rambus Inc, Los Altos, CA 94022 USA

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

10.1109/VLSIC.2008.4585979

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to achieve low jitter despite the slow process and constrained power consumption, including a quad rate clocking with closed-loop quadrature correction, a shared LC-PLL with an octagonal inductor in a three-metal process, and a data-dependent regulator. The transceiver has measured random jitter of 380fs rms at the transmitter output and BER < 10(-14) while consuming 8mW/Gb/s.

引用

页码：128 / 129

页数：2

共 5 条

[1] Replica compensated linear regulators for supply-regulated phase-locked loops [J].