Power and area reduction in CMOS analog fuzzy logic controllers by using a new inference engine structure

被引:5
|
作者
Pirbazari, Mahmoud Mandipour [1 ]
Mesri, Alireza [1 ]
Khoei, Abdollah [1 ]
Hadidi, Khayrollah [1 ]
机构
[1] Urmia Univ, Microelect Res Lab, Orumiyeh, Iran
关键词
Fuzzy hardware; analog CMOS implementation; inference engine; current mode; CURRENT-MODE; CIRCUIT IMPLEMENTATION; HIGH-SPEED; DESIGN;
D O I
10.3233/IFS-151565
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Analog implementation of fuzzy logic controllers (FLCs) is the most efficient method when speed, power, and area are critical. Inference engine (IE) usually takes a large part of total die area when the FLC has a large number of rules. In this paper, a method is proposed to reduce size of the IE in analog implementations of FLCs. Since only a small number of rules may be fired simultaneously, thus a few inference blocks (IBs) may work at the same time in an IE. In the proposed method, reduction in size of the IE is achieved by sharing a few IBs between a large number of rules. To test the proposed method, a standard PLC is designed using both the regular method and the proposed method. By using the proposed method, total power consumption and active area are reduced by factors of 2.31 and 2.15, respectively. Moreover, inference speed is improved by a factor of 3.8 and output error is reduced by a factor of 2.5. All simulations have been performed in HSPICE using level 49 models for 0.35 um CMOS process with a 3.3 V power supply.
引用
收藏
页码:2863 / 2874
页数:12
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