Modified FPGA based Design and Implementation of Reconfigurable FFT Architecture

被引：0

作者：

Bhakthavatchalu, Ramesh

Kripalal, Ammu

Nair, Suchitra

Venugopal, Pallavi

Viswanath, Meera

机构：

来源：

2013 IEEE INTERNATIONAL MULTI CONFERENCE ON AUTOMATION, COMPUTING, COMMUNICATION, CONTROL AND COMPRESSED SENSING (IMAC4S) | 2013年

关键词：

Fast Fourier Transform; Single Path Delay Feedback; R2SPDF; Single ROM Architecture; PIPELINE;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Fast Fourier Transforms, popularly known as FFTs, have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily Area, Memory and Speed. The aim is to build a Reconfigurable Fast Fourier Transform Block which is suitable for any signal processing application, especially for communication blocks such as OFDM receivers. The objective is to design an FFT block that is capable of computing any N-point FFT and employs R2SDF (Radix 2 Single Delay Feedback) architecture with a single ROM. The design has been developed using the hardware description language VHDL on Xilinx xc5vlx110t. The result shows significant reduction in area for this architecture.

引用

页码：818 / 822

页数：5

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