IBIS Simulation Using the Latency Insertion Method (LIM)

被引：3
|
作者：
Schutt-Aine, Jose E. [1 ]
Liu, Ping [2 ]
Tan, Jilin [3 ]
Varma, Ambrish [3 ]
机构：
[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA
[2] Cadence Design Syst, Dept Engn, Shanghai 200233, Peoples R China
[3] Cadence Design Syst, Dept SPB, Chelmsford, MA 01824 USA
来源：
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2013年 / 3卷 / 07期
基金：
美国国家科学基金会;
关键词：
Input/output buffer information specification (IBIS); latency insertion method (LIM); simultaneous switching noise (SSN); transient simulation; FAST TRANSIENT SIMULATION;
D O I：
10.1109/TCPMT.2013.2258716
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
This paper presents an approach for the transient simulation of I/O buffers described by IBIS models. Using the latency insertion method, a formulation can be obtained for the transient behavior of IBIS models combined with external circuitry. The formulation offers better convergence than traditional Newton-Raphson methods and is therefore more robust. The method also implements the BIRD95 and BIRD98 updates that account for predriver current, simultaneous switching noise, and gate modulation effects. Several computer simulations are performed to validate the method.
引用
收藏
页码：1228 / 1236
页数：9
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