Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese

被引：1

作者：

Trong-Thuc Hoang ^{[1
]}

Hong-Kiet Su ^{[1
]}

Hieu-Binh Nguyen ^{[1
]}

Duc-Hung Le ^{[1
]}

Huu-Thuan Huynh ^{[1
]}

Trong-Tu Bui ^{[1
]}

Cong-Kha Pham ^{[2
]}

机构：

[1] Univ Sci, Fac Elect & Telecommun, VNU HCM, Ho Chi Minh City, Vietnam

[2] Univ Electrocommun, Chofu, Tokyo 182, Japan

来源：

IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 14期

关键词：

text-to-speech; TTS; FPGA; real-time; co-processor; Hidden Markov Model; Vietnamese;

D O I：

10.1587/elex.12.20150448

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Although HMM-based TTS has been studied for many years, there are some limitations such as real-time applications based on low-performance and low cost systems. In this paper, we present a design of a TTS co-processor used for HMM-based Text-to-Speech (TTS) hardware systems. Based on a dedicated FPU and resource sharing architecture, the co-processor can compute a lot of DSP algorithms required by HMM at very high speed. The system has been built and verified on the FPGA system with English and Vietnamese languages. The results show that it can compute up to 3 words per second at frequency of 100 MHz with the resources cost about 32,000 logic elements, 19,000 registers, and 957 KB memory.

引用

页数：10

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