A Single-Ended TG Based 8T SRAM Cell With Increased Data Stability and Less Delay

被引:0
作者
Tripathy, Dhananjaya [1 ]
Manasneha, Tarangini [1 ]
Das, Varun [1 ]
机构
[1] Silicon Inst Technol, Dept AE&I, Bhubaneswar, Orissa, India
来源
2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT) | 2017年
关键词
single-ended; TG based 8T; SRAM; data stability; delay; transmission gates;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A single-ended TG based 8-transistor (8T) static random access memory (SRAM) cell having high data stability and reduced delay is presented. The use of feedback cutting scheme reduces the read disturbance and provides better control. The employment of transmission gates (TG) as pass transistors offers less delay in comparison to the conventional CMOS logic. The results after simulation show the delay time to be 191.67 ps. The area and power consumption were found to be 36.380 mu m(2) and 5.105 mu W respectively. The cell was implemented using Cadence UMC 180 nm technology.
引用
收藏
页码:1282 / 1285
页数:4
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