New procedures for identifying undetectable and redundant faults in synchronous sequential circuits

被引：0

作者：

Reddy, SM ^{[1
]}

Pomeranz, I ^{[1
]}

Lin, XJ ^{[1
]}

Basturkmen, NZ ^{[1
]}

机构：

[1] Univ Iowa, Dept Elect & Comp Engn, Iowa City, IA 52242 USA

来源：

17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The procedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.

引用

页码：275 / 281

页数：3

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