Hardware Modelling of JPEG2000 MQ-Encoder

被引：0

作者：

El-Sharkasy, Wael M. ^{[1
]}

Ragab, Mohamed E. ^{[2
]}

机构：

[1] Univ Alexandria, Fac Engn, Dept Elect Engn, Alexandria, Egypt

[2] E JUST, Sch Elect, Dept Comp & Commun, Alexandria, Egypt

来源：

2012 4TH INTERNATIONAL CONFERENCE ON INTELLIGENT AND ADVANCED SYSTEMS (ICIAS), VOLS 1-2 | 2012年

关键词：

JPEG2000; MQ Encoder; Arithmetic Coding; Hardware; VHDL; FPGA; Matlab; IMAGE COMPRESSION STANDARD; JPEG-2000; ARCHITECTURE;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Image compression is one of the most important topics in the field of digital image processing. JPEG2000 is considered as a new image compression standard that offers the requirements needed nowadays. Efficient hardware implementation of this complex standard is a considerable challenge in order to embed the compression engine inside the imaging devices. MQ encoder is one of the main and important modules in the JPEG2000 encoder. This paper proposes a hardware model written in VHDL for this MQ encoder. The design fully achieves all the required performance, identified in the JPEG2000 standard with reasonable hardware specifications and its results are compared with other similar designs.

引用

页码：707 / 712

页数：6

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