Systolic Array Based Architecture for DS Fast Motion Estimation Algorithm

The H.264/AVC video coding standard can achieve up to 50% more compression than its prior video coding standards. From the last two decade, developing systolic array architectures is one of the popular research for VLSI designers because of their inherent regularity and modularity. This paper introduce a 2-D systolic array architecture of diamond search (DS) block-matching algorithm. Until now, no one exiting architectures give the high throughput with 100% hardware utilization. By using, systolic array we have proposed a novel 2-D architecture for DS block-matching algorithm which overcome this problem at the expense of more hardware and power. This is also feasible for variable block size motion estimation and so, we can easily use this in new standards like H.264