Overview of dual damascene integration schemes in Cu BEOL integration

被引：38

作者：

Kriz, J. ^{[1
]}

Angelkort, C. ^{[1
]}

Czekalla, M. ^{[1
]}

Huth, S. ^{[1
]}

Meinhold, D. ^{[1
]}

Pohl, A. ^{[1
]}

Schulte, S. ^{[1
]}

Thamm, A. ^{[1
]}

Wallace, S. ^{[1
]}

机构：

[1] Infineon Technol Dresden, D-01099 Dresden, Germany

来源：

MICROELECTRONIC ENGINEERING | 2008年 / 85卷 / 10期

关键词：

Dual damascene; Trench first; Hardmask; Via first;

D O I：

10.1016/j.mee.2008.05.034

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An overview of different dual damascene approaches is given. Three approaches - trench first, trench first with metal hardmask, and via first - are described in detail. Trench first is the easiest approach but due to its limitation only suitable for wide ground rules with moderate aspect ratios. Via first is capable to run fine pitches and/or higher aspect ratios but has many problems to reach a proper transition between trench and via. With respect to this transition the trench first with metal hardmask concept seems to be advantageous, but it has its own challenges and problems. This article describes our solutions to these problems. (C) 2008 Elsevier B.V. All Fights reserved.

引用

页码：2128 / 2132

页数：5

共 11 条

[1]

COTE W, 2007, AMC

[2]

Dalton TJ, 2004, MAT RES S C, P85

[3] Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology node [J].

Hinsinger, O ;

Fox, R ;

Sabouret, E ;

Goldberg, C ;

Verove, C ;

Besling, W ;

Brun, P ;

Josse, E ;

Monget, C ;

Belmont, O ;

Van Hassel, J ;

Sharma, BG ;

Jacquemin, JP ;

Vannier, P ;

Humbert, A ;

Bunel, D ;

Gonella, R ;

Mastromatteo, E ;

Reber, D ;

Farcy, A ;

Mueller, J ;

Christie, P ;

Nguyen, VH ;

Cregut, C ;

Berger, T .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :317-320

[4] Challenges of damascene etching for copper interconnect [J].

Ho, PKK ;

Zhou, MS ;

Gupta, S .

MULTILEVEL INTERCONNECT TECHNOLOGY III, 1999, 3883 :34-41

[5] A novel approach to dual damascene patterning [J].

Hussein, M ;

Sivakumar, S ;

Brain, R ;

Beattie, B ;

Nguyen, P ;

Fradkin, M .

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, :18-20

[6]

HUSSEIN M, 2001, Patent No. 6329118

[7]

LEE KW, 2003, VLSI

[8]

MCGAHAY V, 2002, ULSI, P3

[9] Aluminum dual damascene metallization for 0.175 μm DRAM generations and beyond -: (invited) [J].

Schnabel, RF ;

Clevenger, LA ;

Costrini, G ;

Dobuzinsky, DM ;

Filippi, R ;

Gambino, J ;

Lee, GY ;

Iggulden, RC ;

Lin, C ;

Lu, ZG ;

Ning, XJ ;

Ramachandran, R ;

Ronay, M ;

Többen, D ;

Weber, SJ .

MICROELECTRONIC ENGINEERING, 2000, 50 (1-4) :265-270

[10] Dual Damascene architectures evaluation for the 0.18 μm technology and below [J].

Vérove, C ;

Descouts, B ;

Gayet, P ;

Guillermet, M ;

Sabouret, E ;

Spinelli, P ;

Van der Vegt, E .

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, :267-269

← 1 2 →