Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region

被引：17

作者：

Tai, Ya-Hsiang ^{[1
,2
]}

Huang, Shih-Che ^{[1
,3
]}

Chen, Po-Ting ^{[1
,2
]}

机构：

[1] Natl Chiao Tung Univ, Dept Photon, Hsinchu 30010, Taiwan

[2] Natl Chiao Tung Univ, Display Inst, Hsinchu 30010, Taiwan

[3] Natl Chiao Tung Univ, Inst Electroopt Engn, Hsinchu 30010, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 03期

关键词：

AC stress; dynamic stress; poly-Si thin-film transistors (TFTs); reliability; RELIABILITY;

D O I：

10.1109/LED.2008.2010784

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large Voltage drop across the source and drain junctions.

引用

页码：231 / 233

页数：3

共 7 条

[1]

ALEXANDER C, 2004, FUNDAMENTALS ELECT C, P383

[2]

HUANG SC, 2007, P IDMC, P134

[3] Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress [J].