Enhancing microprocessor immunity to power supply noise with clock-data compensation

被引:74
作者
Wong, KL [1 ]
Rahat-Arabi, T
Ma, M
Taylor, G
机构
[1] Intel Corp, Technol Mfg Grp, Hillsboro, OR 97124 USA
[2] Intel Corp, Mobil Grp, Beaverton, OR 97006 USA
关键词
clock-data compensation; Clock distribution; clock jitter; data-clock synchronization; Fmax; microprocessor speed; package resonance; power delivery; power supply noise;
D O I
10.1109/JSSC.2006.870925
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach.
引用
收藏
页码:749 / 758
页数:10
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