共 50 条
- [32] Sensitivity Analysis of Through-Silicon Via (TSV) Interconnects for 3-D ICs 2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
- [33] 3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (02): : 221 - 228
- [34] Coupling Analysis of Through-Silicon Via (TSV) Arrays in Silicon Interposers for 3D Systems 2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2011, : 16 - 21
- [35] An Alternative Approach to Backside Via Reveal (BVR) for a Via-Middle Through-Silicon Via (TSV) Flow 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 551 - 554
- [36] Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (01): : 138 - 152
- [37] Performance Comparison and Analysis by Electrical Measurement for Through-silicon vias (TSV) in Wafer Level Package 2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
- [39] Thermally Induced Deformation Measurement of Through-Silicon Via (TSV) Structures using an Atomic Force Microscope (AFM) Moire Method 2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2012,