A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

被引:35
作者
Wu, Chao [1 ]
Yuan, Jie [1 ]
机构
[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Peoples R China
关键词
Calibration technique; high-speed analog-todigital converter (ADC); loop-unrolled successive approximation register (SAR); open-loop multiplying digital-to-analog converter (MDAC); pipelined-SAR ADC; CMOS ADC; 10-BIT; 6-BIT; YIELD; SFDR;
D O I
10.1109/JSSC.2018.2886327
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Compared to pipelined analog-to-digital converters (ADCs), pipelined- successive approximation register (SAR) ADCs have been actively explored for better energy efficiency in recent years. Nonetheless, the pipelined-SAR architecture inherently limits the sampling speed of the ADC due to the slow operation of the first SAR ADC, which becomes an increasingly important limitation with the recent expansion of high-speed applications. In this paper, we introduce our new design of a pipelined-SAR ADC to enable faster speed. New loop-unrolled architecture with the split capacitor is used for the first SAR ADC to improve the speed. A resistive open-loop multiplying digital to -analog converter with a new calibration scheme is designed to reduce the power consumption at high speed. As a result, the 65-nm design can achieve 300-MS/s sampling rate with a single channel. It is among the fastest pipelined-SAR ADC design so far. The peak signal-to-noise-and-distortion ratio is 63.6 dI3 with a 10-MHz input. It consumes 12.5-mW power from a 1.2-V supply to achieve a power efficiency of 34 fJ/conversion-step.
引用
收藏
页码:1446 / 1454
页数:9
相关论文
共 32 条
[1]   A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter [J].
Ali, Ahmed M. A. ;
Dillon, Christopher ;
Sneed, Robert ;
Morgan, Andrew S. ;
Bardsley, Scott ;
Komblum, John ;
Wu, Lu .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1846-1855
[2]   A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers [J].
Boo, Hyun H. ;
Boning, Duane S. ;
Lee, Hae-Seung .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (12) :2912-2921
[3]   A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS [J].
Chen, Shuo-Wei Michael ;
Brodersen, Robert W. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2669-2680
[4]  
Devarajan Siddharth, 2009, 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009), P86, DOI 10.1109/ISSCC.2009.4977320
[5]  
Devarajan S, 2017, ISSCC DIG TECH PAP I, P288, DOI 10.1109/ISSCC.2017.7870374
[6]  
Furuta Masanori, 2010, 2010 IEEE International Solid-State Circuits Conference (ISSCC), P382, DOI 10.1109/ISSCC.2010.5433968
[7]   A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique [J].
Furuta, Masanori ;
Nozawa, Mai ;
Itakura, Tetsuro .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (06) :1360-1370
[8]   A highly integrated CMOS analog baseband transceiver with 180 MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs [J].
Gulati, Kush ;
Peng, Mark Shane ;
Pulincherry, Anurag ;
Munoz, Carlos E. ;
Lugin, Mike ;
Bugeja, Alex R. ;
Li, Jipeng ;
Chandrakasan, Anantha P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1856-1866
[9]   A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation [J].
Huang, Hai ;
Xu, Hongda ;
Elies, Brian ;
Chiu, Yun .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (12) :3235-3247
[10]   A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS [J].
Jiang, Tao ;
Liu, Wing ;
Zhong, Freeman Y. ;
Zhong, Charlie ;
Hu, Kangmin ;
Chiang, Patrick Yin .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (10) :2444-2453