The Influence of Hysteresis Voltage on Single Event Transients in a 65nm CMOS High Speed Comparator

被引：0

作者：

Nawi, Illani Mohd ^{[1
]}

Halak, Basel ^{[1
]}

Zwolinski, Mark ^{[1
]}

机构：

[1] Univ Southampton, Elect & Comp Sci, Southampton SO17 1BJ, Hants, England

来源：

2016 21TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) | 2016年

关键词：

Single event transients; comparator-with-hysteresis; Schmitt trigger; high speed; trade-offs;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hysteresis in a comparator improves the input noise immunity, but can also cause analogue single event transients (ASETs) to be captured. For example, compared to a hysteresis-free comparator, a comparator with a hysteresis voltage of 8 mV, takes an additional 40 ns to recover. As the requirement for noise immunity increases, the vulnerability of a comparator with hysteresis to ASETs worsens. The reliability also worsens for higher sampling frequencies and lower differential input voltage amplitudes. This paper investigates the trade-off between noise immunity and reliability in a 65nm CMOS comparator.

引用

页数：2

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