A design environment for high-throughput low-power dedicated signal processing systems

被引：34
作者：
Davis, WR [1 ]
Zhang, N
Camera, K
Markovic, D
Smilkstein, T
Ammer, MJ
Yeo, EL
Augsburger, S
Nikolic, B
Brodersen, RW
机构：
[1] Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA
[2] Atheros Commun Inc, Sunnyvale, CA 94085 USA
[3] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94704 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2002年 / 37卷 / 03期
关键词：
application specific integrated circuits; design automation; design methodology; integrated circuit design; parallel architectures; system analysis and design;
D O I：
10.1109/4.987095
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined dataflow graph and floorplan description drives automatic layout generation with commercial CAD tools. Automatic characterization of layout improves system-level estimates. Simplified physical design methodologies for low supply voltages are discussed. The flow is demonstrated on a 300-k transistor test-chip, a time-division multiple-access base-band receiver, and a soft-output Viterbi decoder. An example of architectural comparison of energy efficiency is presented.
引用
收藏
页码：420 / 431
页数：12
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