Design and Implementation of Fourth Arm for Elimination of Bearing Current in NPC-MLI-Fed Induction Motor Drive

被引:38
作者
Bharatiraja, C. [1 ]
Selvaraj, Raghu [2 ]
Chelliah, Thanga Raj [2 ]
Munda, Josiah L. [3 ]
Tariq, Mohd [4 ]
Maswood, Ali I. [4 ]
机构
[1] Sri Ramaswami Mem SRM Univ, Dept Elect Engn, Madras 603203, Tamil Nadu, India
[2] Indian Inst Technol Roorkee, Dept Water Resources Dev & Management, Roorkee 247667, Uttar Pradesh, India
[3] Tshwane Univ Technol, Dept Elect Engn, ZA-0183 Pretoria, South Africa
[4] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
关键词
Bearing current; common-mode voltage (CMV); fourth arm circuitry (FAC); neutral-point-clamped-multilevel inverter (NPC-MLI); switching states; COMMON-MODE VOLTAGE; PWM INVERTER; ASD APPLICATIONS; SYSTEMS; EMI; MITIGATION; MACHINES; OVERVOLTAGES; MODULATION; PARAMETERS;
D O I
10.1109/TIA.2017.2759204
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The exploration result of an increase in power electronics converter-based variable-speed drives for industrial applications reveals the impact of inverter-induced bearing current on the prevailing electric machine failure. The bearing current associated with drive systems is concerned about operating frequencies of the solid-state semiconductor switches, which may cause the electrostatic charge between stator and rotor, which eventually causes damage to windings and bearings. The various techniques comprised in the literature to suppress bearing currents are filter design, switching redundancy, common-mode circuitry, isolated grounding scheme, and grounding the motor shaft. From the literature, the pulse-width modulation inverter-injected common-mode voltage (CMV) is the main source of common-mode current, which causes the bearing current. Hence, the elimination of CMV paves the way for eliminating bearing current of the machine. This paper presents an innovative solution to suppress bearing currents by aiding a fourth arm circuitry to acquire near to zero potential (zero CMV) at machine neutral point. All the proposed circuitry and algorithm are simulated using MATLAB/Simulink and validation is done through a 2.5-kW neutral-point-clamped-multilevel inverter laboratory prototype using a Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 digital signal processor-field programmable gate array board.
引用
收藏
页码:745 / 754
页数:10
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