A Novel Leakage Power Reduction Technique for Nano-Scaled CMOS Digital Integrated Circuits

被引：0

作者：

Aghababa, Hossein ^{[1
]}

Kolahdouz, Mohammadreza ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran, Iran

来源：

PROCEEDINGS OF 2016 26TH INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) | 2016年

关键词：

Leakage minimization; manufacturing process variations; low-power design; variability reduction; CMOS Integrated Circuit; MODEL;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

In this paper, we present a method to improve the efficacy of a famous leakage reduction technique known as gate length biasing. In proposed method, gate length biasing is combined with progressive sizing. The method greatly reduces both the leakage power consumption and its spread without a significant delay overhead. In addition, it does not increase the complexity of the design. To assess the efficacy of this method, leakage power consumptions of several benchmark circuits optimized by our method and conventional gate length biasing techniques are compared. The circuits are implemented in a 65nm standard CMOS technology. The simulation results reveal that the proposed method reduces the nominal standby leakage power consumption and its spread by 20% and 18%, respectively, with 2-6% delay increase on average.

引用

页码：268 / 274

页数：7

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