Plasma-Induced Defect-Site Generation in Si Substrate and Its Impact on Performance Degradation in Scaled MOSFETs

被引：35

作者：

Eriguchi, Koji ^{[1
]}

Nakakubo, Yoshinori ^{[1
]}

Matsuda, Asahiko ^{[1
]}

Takao, Yoshinori ^{[1
]}

Ono, Kouichi ^{[1
]}

机构：

[1] Kyoto Univ, Kyoto 6068501, Japan

来源：

IEEE ELECTRON DEVICE LETTERS | 2009年 / 30卷 / 12期

基金：

日本学术振兴会;

关键词：

Capacitance; defect site; device simulation; drain current; plasma-induced damage (PID); DAMAGE;

D O I：

10.1109/LED.2009.2033726

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Plasma-induced ion-bombardment damage was studied in terms of defect sites created underneath the exposed Si surface. From the shift of capacitance-voltage (C-V) curves, the defect sites were found to capture carriers (being negatively charged in the case of an Ar plasma exposure). This results in a change of the effective impurity-doping density and the profile. We also report that the defect density depends on the energy of ions from plasma. A simplified and quantitative model is proposed for the drain-current degradation induced by the series-resistance increase by the damage. The relationship derived between the defect density and the drain-current degradation is verified by device simulations. The proposed model is useful to predict the device performance change from plasma process parameters.

引用

页码：1275 / 1277

页数：3

共 17 条

[1]

Eriguchi K, 2008, INT EL DEVICES MEET, P443

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