Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

被引：9

作者：

Bailey, B ^{[1
]}

Metayer, A ^{[1
]}

Svrcek, B ^{[1
]}

Tendolkar, N ^{[1
]}

Wolf, E ^{[1
]}

Fiene, E ^{[1
]}

Alexander, M ^{[1
]}

Woltenberg, R ^{[1
]}

Raina, R ^{[1
]}

机构：

[1] Motorola Inc, Somerset Design Ctr, Austin, TX 78729 USA

来源：

INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/TEST.2002.1041808

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the DFT techniques used in Motorola's high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to I GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2% stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.

引用

页码：574 / 583

页数：10

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