A second order mixed-mode charge pump scheme for low phase/duty error and low power consumption

被引：0
作者：
Kim, Kyu-Hyoun
Chung, In-Young
机构：
[1] Gyeongsang Natl Univ, Dept Elect Engn, Jinju, South Korea
[2] Gyeongsang Natl Univ, ERI, Jinju, South Korea
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 2007年 / E90C卷 / 01期
关键词：
second order; charge pump; phase error; DLL; duty cycle corrector; (DCC);
D O I：
10.1093/ietele/e90-c.1.208
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A second order charge pump (SOCP) scheme is proposed in this letter. Compared with the conventional single charge pump, the second order charge pump does not suffer phase errors caused by the output voltage dependent current mismatches. Also, the second order charge pump can be implemented in a mixed-mode type, enabling the fast lock and the various operation modes simultaneously. The proposed SOCP has been adopted into the duty cycle corrector (DCC) loops of DDR2 DRAM, and shows a much widened correction range owing to the removal of the parasitic effects.
引用
收藏
页码：208 / 211
页数：4
相关论文
共 6 条
[1]   Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications [J].
Djahanshahi, H ;
Salama, CAT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (06) :847-855
[2]   Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM application [J].
Kim, KH ;
Cho, GH ;
Lee, JB ;
Cho, SI .
2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :287-288
[3]  
LEE JB, 2001, IEEE INT SOL STAT CI, P68
[4]   A 2.5-V CMOS DELAY-LOCKED LOOP FOR AN 18-MBIT, 500-MEGABYTE/S DRAM [J].
LEE, TH ;
DONNELLY, KS ;
HO, JTC ;
ZERBE, J ;
JOHNSON, MG ;
ISHIKAWA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1491-1496
[5]  
Razavi B., 2017, DESIGN ANALOG CMOS I
[6]   A wide-range multiphase delay-locked loop using mixed-mode VCDLs [J].
Yang, RJ ;
Liu, SI .
IEICE TRANSACTIONS ON ELECTRONICS, 2005, E88C (06) :1248-1252
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