Flexible VLIW processor based on FPGA for efficient embedded real-time image processing

被引:5
作者
Brost, Vincent [1 ]
Yang, Fan [1 ]
Meunier, Charles [1 ]
机构
[1] Univ Burgundy, CNRS Lab LE2I 6306, F-21078 Dijon, France
关键词
Rapid prototyping; System design; VLIW processor; FPGA; Real-time image processing; Biometric system; ARCHITECTURE; DESIGN;
D O I
10.1007/s11554-012-0321-2
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Modern field programmable gate array (FPGA) chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance VLIW (very long instruction word) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient ILP (instruction-level parallelism) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors to shorten the development cycle, and to use the powerful FPGA resources to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allows exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated using the proposed development cycle. We also realized the rapid prototyping of embedded contactless palmprint extraction on an FPGA Virtex-6 based board for a biometric application and obtained a processing time of 145.6 ms per image. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability.
引用
收藏
页码:47 / 59
页数:13
相关论文
共 28 条
[1]   Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems [J].
Aguirre, MA ;
Tombs, JN ;
Baena-Lecuyer, V ;
Mora, JL ;
Carrasco, JM ;
Torralba, A ;
Franquelo, LG .
MICROPROCESSORS AND MICROSYSTEMS, 2005, 29 (2-3) :75-85
[2]   FPGA-based IP cores implementation for face recognition using dynamic partial reconfiguration [J].
Ahmad, Afandi ;
Amira, Abbes ;
Nicholl, Paul ;
Krill, Benjamin .
JOURNAL OF REAL-TIME IMAGE PROCESSING, 2013, 8 (03) :327-340
[3]  
[Anonymous], 2009, VIRTEX 6 XILINK DS15
[4]   FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision [J].
Botella, Guillermo ;
Antonio Martin H, Jose ;
Santos, Matilde ;
Meyer-Baese, Uwe .
SENSORS, 2011, 11 (08) :8164-8179
[5]   Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing [J].
Bravo, Ignacio ;
Balinas, Javier ;
Gardel, Alfredo ;
Lazaro, Jose L. ;
Espinosa, Felipe ;
Garcia, Jorge .
SENSORS, 2011, 11 (03) :2282-2303
[6]  
Brost V., 2007, J ELECT IMAGING SPIE, V16
[7]   A modular VLIW processor [J].
Brost, Vincent ;
Yang, Fan ;
Paindavoine, Michel .
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, :3968-3971
[8]   Fast buffering for FPGA implementation of vision-based object recognition systems [J].
Cao, Tam P. ;
Elton, Darrell ;
Deng, Guang .
JOURNAL OF REAL-TIME IMAGE PROCESSING, 2012, 7 (03) :173-183
[9]   Processing element allocation and dynamic scheduling codesign for multi-function SoCs [J].
Chen, Ya-Shu ;
Shih, Chi-Sheng ;
Kuo, Tei-Wei .
REAL-TIME SYSTEMS, 2010, 44 (1-3) :72-104
[10]  
Cyllenhaal J., 1996, IMPACT963 U ILL