Dynamic fraction control bus: New SOC on-chip communication architecture design

被引：0
|
作者：
Wang, N [1 ]
Bayoumi, MA [1 ]
机构：
[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
As technology scales toward deeper submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible. The on-chip communication architecture is becoming the bottleneck for these System-on-a-Chips (SOC). The conventional communication architectures all have their limitations. This paper presents new communication architectures, Static Fraction Control Bus (SFCB) and Dynamic Fraction Control Bus (DFCB), to address the shortcomings of these conventional communication architectures.
引用
收藏
页码：199 / 202
页数：4
相关论文
共 50 条
  • [21] Design of On-Chip Bus with OCP Interface
    Chang, Chin-Yao
    Chang, Yi-Jiun
    Lee, Kuen-Jong
    Yeh, Jen-Chieh
    Lin, Shih-Yin
    Ma, Jui-Liang
    2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 211 - 214
  • [22] Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design
    Cho, Y
    Lee, G
    Yoo, S
    Choi, K
    Zergainoh, NE
    DESIGNERS FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2003, : 132 - 137
  • [23] Joint equalization and coding for on-chip bus communication
    Sridhara, Srinivasa R.
    Balamurugan, Ganesh
    Shanbhag, Naresh R.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (03) : 314 - 318
  • [24] Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design
    Cho, Y
    Lee, G
    Choi, K
    Yoo, S
    Zergainoh, NE
    EMBEDDED SOFTWARE FOR SOC, 2003, : 125 - 136
  • [25] Joint equalization and coding for on-chip bus communication
    Sridhara, SR
    Shanbhag, NR
    Balamurugan, G
    6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 642 - 647
  • [26] Energy/Area/Delay tradeoffs in the physical design of on-chip segmented bus architecture
    Guo, Jin
    Papanikolaou, Antonis
    Zhang, Hao
    Catthoor, Francky
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (08) : 941 - 944
  • [27] <bold>ENERGY EFFICIENT STATISTICAL ON-CHIP COMMUNICATION BUS SYNTHESIS FOR A RECONFIGURABLE ARCHITECTURE</bold>
    Pandey, Sujan
    Glesner, Manfred
    2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 169 - 174
  • [28] An architecture and compiler for scalable on-chip communication
    Liang, H
    Laffely, A
    Srinivasan, S
    Tessier, R
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (07) : 711 - 726
  • [29] Modelling and refinement of an on-chip communication architecture
    Plosila, J
    Liljeberg, P
    Isoaho, J
    FORMAL METHODS AND SOFTWARE ENGINEERING, PROCEEDINGS, 2005, 3785 : 219 - 234
  • [30] Architecture and synthesis for on-chip multicycle communication
    Cong, J
    Fan, YP
    Han, GL
    Yang, X
    Zhang, ZR
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (04) : 550 - 564
12345