Dynamic fraction control bus: New SOC on-chip communication architecture design

被引：0

作者：

Wang, N ^{[1
]}

Bayoumi, MA ^{[1
]}

机构：

[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As technology scales toward deeper submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible. The on-chip communication architecture is becoming the bottleneck for these System-on-a-Chips (SOC). The conventional communication architectures all have their limitations. This paper presents new communication architectures, Static Fraction Control Bus (SFCB) and Dynamic Fraction Control Bus (DFCB), to address the shortcomings of these conventional communication architectures.

引用

页码：199 / 202

页数：4

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